This is not required for the prototype and may not be understood by the tools.Īs with BIST, clock gating can be inferred by SoC tools but is often written directly into the RTL.
#Synplify pro stop clock inference full
Instantiations of SoC memory will not be understood by the FPGA tool flow.įrom simple DesignWare macros up to full CPU sub-systems, if the source RTL for the IP is not available then we will need to insert an equivalent.īuilt-in self test (BIST) and other test-related circuitry is mostly inferred during the SoC flow but some is also instantiated directly into the RTL. Leaf cells from the SoC library are instantiated into the RTL, for whatever reason, and they will also not be understood by the FPGA tool flow. These will not be understood by the FPGA tool flow. The design is not available in RTL form, but only as a mapped netlist of SoC library cells. Instantiations of SoC pads will not be understood by the FPGA tool flow. Table 15: SoC design elements that might require RTL changes Top-level pads Obviously care and revision control methods should be employed to avoid error but in the end, we are probably going to be changing the RTL at some time. To facilitate the SoC design modifications, we may make copies of affected source files, edit them and then simply replace the originals for the duration of the prototyping project.
#Synplify pro stop clock inference how to
The typical design variations, and examples of how to best handle them, are discussed in more detail later in this chapter. Design variations are also caused by limitations in the prototyping platform, tweaking for higher performance and debug instrumentation. The design variations are typically due to design elements found in the SoC technology which are not available in, or suitable for FPGA technology.
While the aim is always to prototype the SoC source RTL in its original form, early on in the prototyping effort it typically becomes evident that the SoC design will have to be modified for it to fit into the prototyping system. We also revisit the implementation process and common tools outlined in chapter 3 in order to accomplish the best system performance. We cover SoC library cells, memories and clock gating in depth. It covers SoC design-related issues, techniques to make the design prototyping friendly and how to use FPGA special-purpose resources. This chapter describes the main prototyping challenges, common practices and the process of taking an SoC design into the FPGA-based prototyping system.
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